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this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 1 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 features ? single power supply operation - full voltage range:1.65-1.95 volt for read and write operations. - ideal for battery-powered applications. ? high performance - access times as fast as 70 ns ? low power consumption (typical values at 5 mhz) - 5 ma typical active read current - 15 ma typical program/erase current - 0.2 a typical standby current ? uniform sector architecture: - 512 sectors of 2-kword - 32 blocks of 32-kword - any sector or block can be erased individually ? wp#/acc input pin: - write protect (wp#) function allows protection the first or last blocks, regardless of block protect status - acceleration (acc) function acceleration program timing. ? block group protection: - hardware lo cking of blocks to prevent program or erase operations within individual blocks - additionally, temporary block unprotect allows code changes in previously locked blocks. ? high performance program/erase speed - word program time: 8s typical - sector erase time: 90ms typical - block erase time: 180ms typical - chip erase time: 4s typical ? jedec standard embedded erase and program algorithms ? jedec standard data # polling and toggle bits feature ? single sector, block and chip erase ? chip unprotect mode ? erase suspend / resume modes: read or program another sector/block during erase suspend mode ? low vcc write inhibit < 1.2v ? minimum 100k endurance cycle ? package options - 48-ball 6mm x 8mm tfbga - 48-ball 4mm x 6mm wfbga ? industrial temperature range general description the en39sl160ah/l is a 16-megabit, electrically erasable, read/write non-volatile flash memory, organized as 1,048,576 words. any word can be programmed typically in 8s.the en39sl160ah/l features 1.8v voltage read and write operation, with access time as fast as 70ns to eliminate the need for wait statements in high-performance microprocessor systems. the en39sl160ah/l has separate output enable (oe#), chip enable (ce#), and write enable (we#) controls, which eliminate bus contention issues. this device is designed to allow either single sector/block or full chip erase operation, where each block can be individually protected against program/erase operations or temporarily unprotected to erase or program. the device can sustain a minimum of 100k program/erase cycles on each sector or block. en39sl160ah/l 16 megabit (1024k x 16-bit) flas h memory with 4kbytes uniform sector, cmos 1.8 volt-only
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 2 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 connection diagrams tfbga top view, balls facing down
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 3 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 a6 a2 b6 a4 c6 a6 d6 a17 e6 nc f6 nc g6 we# h6 j6 a9 k6 a11 a5 a1 b5 a3 c5 a7 d5 wp #/a h5 nc j5 a10 k5 a13 l5 a14 a4 a0 b4 a5 c4 a18 j4 a8 k4 a12 l4 a15 a3 ce# b3 dq8 c3 dq10 j3 dq4 k3 dq11 l3 a16 a2 v ss b2 oe# c2 dq9 d2 a19 h2 nc j2 dq5 k2 dq6 l2 dq7 b1 dq0 c1 dq1 d1 dq2 e1 dq3 f1 v dd g1 dq12 h1 dq13 j1 dq14 k1 dq15 l1 v ss wfbga top view, balls facing down wp#/acc reset#
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 4 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 1. pin description figure 1. logic diagram pin name function a0-a19 addresses dq0-dq15 16 data inputs/outputs ce# chip enable oe# output enable reset# hardware reset pin we# write enable wp#/acc hardware write protect/acceleration pin vcc supply voltage (1.65-1.95v) vss ground nc not connected to anything en39sl160ah/l dq0 ? dq15 a0 - a19 we# ce# oe # reset# wp # / ac c
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 5 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 2. uniform sector / block architecture (block 24 ~ 31) address range block sector (x16) sector size (kwords) a19 a18 a17 a16 a15 a14 a13 a12 a11 511 0ff800h-0fffffh 2 1 1 1 1 1 1 1 1 1 510 0ff000h-0ff7ffh 2 1 1 1 1 1 1 1 1 0 509 0fe800h-0fefffh 2 1 1 1 1 1 1 1 0 1 508 0fe000h-0fe7ffh 2 1 1 1 1 1 1 1 0 0 507 0fd800h-0fdfffh 2 1 1 1 1 1 1 0 1 1 506 0fd000h-0fd7ffh 2 1 1 1 1 1 1 0 1 0 505 0fc800h-0fcfffh 2 1 1 1 1 1 1 0 0 1 504 0fc000h-0fc7ffh 2 1 1 1 1 1 1 0 0 0 503 0fb800h-0fbfffh 2 1 1 1 1 1 0 1 1 1 502 0fb000h-0fb7ffh 2 1 1 1 1 1 0 1 1 0 501 0fa800h-0fafffh 2 1 1 1 1 1 0 1 0 1 500 0fa000h-0fa7ffh 2 1 1 1 1 1 0 1 0 0 499 0f9800h-0f9fffh 2 1 1 1 1 1 0 0 1 1 498 0f9000h-0f97ffh 2 1 1 1 1 1 0 0 1 0 497 0f8800h-0f8fffh 2 1 1 1 1 1 0 0 0 1 31 496 0f8000h-0f87ffh 2 1 1 1 1 1 0 0 0 0 495 0f7800h-0f7fffh 2 1 1 1 1 0 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 30 480 0f0000h-0f07ffh 2 1 1 1 1 0 0 0 0 0 479 0ef800h-0effffh 2 1 1 1 0 1 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 29 464 0e8000h-0e87ffh 2 1 1 1 0 1 0 0 0 0 463 0e7800h-0e7fffh 2 1 1 1 0 0 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 28 448 0e0000h-0e07ffh 2 1 1 1 0 0 0 0 0 0 447 0df800h-0dffffh 2 1 1 0 1 1 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 27 432 0d8000h-0d87ffh 2 1 1 0 1 1 0 0 0 0 431 0d7800h-0d7fffh 2 1 1 0 1 0 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 26 416 0d0000h-0d07ffh 2 1 1 0 1 0 0 0 0 0 415 0cf800h-0cffffh 2 1 1 0 0 1 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 25 400 0c8000h-0c87ffh 2 1 1 0 0 1 0 0 0 0 399 0c7800h-0c7fffh 2 1 1 0 0 0 1 1 1 1 398 0c7000h-0c77ffh 2 1 1 0 0 0 1 1 1 0 397 0c6800h-0c6fffh 2 1 1 0 0 0 1 1 0 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 386 0c1000h-0c17ffh 2 1 1 0 0 0 0 0 1 0 385 0c0800h-0c0fffh 2 1 1 0 0 0 0 0 0 1 24 384 0c0000h-0c07ffh 2 1 1 0 0 0 0 0 0 0
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 6 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 2. uniform sector / block architecture (block 16 ~ 23) address range block sector (x16) sector size (kwords) a19 a18 a17 a16 a15 a14 a13 a12 a11 383 0bf800h-0bffffh 2 1 0 1 1 1 1 1 1 1 382 0bf000h-0bf7ffh 2 1 0 1 1 1 1 1 1 0 381 0be800h-0befffh 2 1 0 1 1 1 1 1 0 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 370 0b9000h-0b97ffh 2 1 0 1 1 1 0 0 1 0 369 0b8800h-0b8fffh 2 1 0 1 1 1 0 0 0 1 23 368 0b8000h-0b87ffh 2 1 0 1 1 1 0 0 0 0 367 0b7800h-0b7fffh 2 1 0 1 1 0 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 22 352 0b0000h-0b07ffh 2 1 0 1 1 0 0 0 0 0 351 0af800h-0affffh 2 1 0 1 0 1 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 21 336 0a8000h-0a87ffh 2 1 0 1 0 1 0 0 0 0 335 0a7800h-0a7fffh 2 1 0 1 0 0 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 20 320 0a0000h-0a07ffh 2 1 0 1 0 0 0 0 0 0 319 09f800h-09ffffh 2 1 0 0 1 1 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 19 304 098000h-0987ffh 2 1 0 0 1 1 0 0 0 0 303 097800h-097fffh 2 1 0 0 1 0 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 18 288 090000h-0907ffh 2 1 0 0 1 0 0 0 0 0 287 08f800h-08ffffh 2 1 0 0 0 1 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 17 272 088000h-0887ffh 2 1 0 0 0 1 0 0 0 0 271 087800h-087fffh 2 1 0 0 0 0 1 1 1 1 270 087000h-0877ffh 2 1 0 0 0 0 1 1 1 0 269 086800h-086fffh 2 1 0 0 0 0 1 1 0 1 268 086000h-0867ffh 2 1 0 0 0 0 1 1 0 0 267 085800h-085fffh 2 1 0 0 0 0 1 0 1 1 266 085000h-0857ffh 2 1 0 0 0 0 1 0 1 0 265 084800h-084fffh 2 1 0 0 0 0 1 0 0 1 264 084000h-0847ffh 2 1 0 0 0 0 1 0 0 0 263 083800h-083fffh 2 1 0 0 0 0 0 1 1 1 262 083000h-0837ffh 2 1 0 0 0 0 0 1 1 0 261 082800h-082fffh 2 1 0 0 0 0 0 1 0 1 260 082000h-0827ffh 2 1 0 0 0 0 0 1 0 0 259 081800h-081fffh 2 1 0 0 0 0 0 0 1 1 258 081000h-0817ffh 2 1 0 0 0 0 0 0 1 0 257 080800h-080fffh 2 1 0 0 0 0 0 0 0 1 16 256 080000h-0807ffh 2 1 0 0 0 0 0 0 0 0
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 7 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 2. uniform sector / block architecture (block 8 ~ 15) address range block sector (x16) sector size (kwords) a19 a18 a17 a16 a15 a14 a13 a12 a11 255 07f800h-07ffffh 2 0 1 1 1 1 1 1 1 1 254 07f000h-07f7ffh 2 0 1 1 1 1 1 1 1 0 253 07e800h-07efffh 2 0 1 1 1 1 1 1 0 1 252 07e000h-07e7ffh 2 0 1 1 1 1 1 1 0 0 251 07d800h-07dfffh 2 0 1 1 1 1 1 0 1 1 250 07d000h-07d7ffh 2 0 1 1 1 1 1 0 1 0 249 07c800h-07cfffh 2 0 1 1 1 1 1 0 0 1 248 07c000h-07c7ffh 2 0 1 1 1 1 1 0 0 0 247 07b800h-07bfffh 2 0 1 1 1 1 0 1 1 1 246 07b000h-07b7ffh 2 0 1 1 1 1 0 1 1 0 245 07a800h-07afffh 2 0 1 1 1 1 0 1 0 1 244 07a000h-07a7ffh 2 0 1 1 1 1 0 1 0 0 243 079800h-079fffh 2 0 1 1 1 1 0 0 1 1 242 079000h-0797ffh 2 0 1 1 1 1 0 0 1 0 241 078800h-078fffh 2 0 1 1 1 1 0 0 0 1 15 240 078000h-0787ffh 2 0 1 1 1 1 0 0 0 0 239 077800h-077fffh 2 0 1 1 1 0 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 14 224 070000h-0707ffh 2 0 1 1 1 0 0 0 0 0 223 06f800h-06ffffh 2 0 1 1 0 1 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 13 208 068000h-0687ffh 2 0 1 1 0 1 0 0 0 0 207 067800h-067fffh 2 0 1 1 0 0 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 12 192 060000h-0607ffh 2 0 1 1 0 0 0 0 0 0 191 05f800h-05ffffh 2 0 1 0 1 1 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 11 176 058000h-0587ffh 2 0 1 0 1 1 0 0 0 0 175 057800h-057fffh 2 0 1 0 1 0 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 10 160 050000h-0507ffh 2 0 1 0 1 0 0 0 0 0 159 04f800h-04ffffh 2 0 1 0 0 1 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 9 144 048000h-0487ffh 2 0 1 0 0 1 0 0 0 0 143 047800h-047fffh 2 0 1 0 0 0 1 1 1 1 142 047000h-0477ffh 2 0 1 0 0 0 1 1 1 0 141 046800h-046fffh 2 0 1 0 0 0 1 1 0 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 130 041000h-0417ffh 2 0 1 0 0 0 0 0 1 0 129 040800h-040fffh 2 0 1 0 0 0 0 0 0 1 8 128 040000h-0407ffh 2 0 1 0 0 0 0 0 0 0
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 8 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 2. uniform sector / block architecture (block 0 ~ 7) address range block sector (x16) sector size (kwords) a19 a18 a17 a16 a15 a14 a13 a12 a11 127 03f800h-03ffffh 2 0 0 1 1 1 1 1 1 1 126 03f000h-03f7ffh 2 0 0 1 1 1 1 1 1 0 125 03e800h-03efffh 2 0 0 1 1 1 1 1 0 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 114 039000h-0397ffh 2 0 0 1 1 1 0 0 1 0 113 038800h-038fffh 2 0 0 1 1 1 0 0 0 1 7 112 038000h-0387ffh 2 0 0 1 1 1 0 0 0 0 111 037800h-037fffh 2 0 0 1 1 0 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 6 96 030000h-0307ffh 2 0 0 1 1 0 0 0 0 0 95 02f800h-02ffffh 2 0 0 1 0 1 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 5 80 028000h-0287ffh 2 0 0 1 0 1 0 0 0 0 79 027800h-027fffh 2 0 0 1 0 0 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 4 64 020000h-0207ffh 2 0 0 1 0 0 0 0 0 0 63 01f800h-01ffffh 2 0 0 0 1 1 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 3 48 018000h-0187ffh 2 0 0 0 1 1 0 0 0 0 47 017800h-017fffh 2 0 0 0 1 0 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 2 32 010000h-0107ffh 2 0 0 0 1 0 0 0 0 0 31 00f800h-00ffffh 2 0 0 0 0 1 1 1 1 1 ?. ?. 2 ?. ?. ?. ?. ?. ?. ?. ?. ?. 1 16 008000h-0087ffh 2 0 0 0 0 1 0 0 0 0 15 007800h-007fffh 2 0 0 0 0 0 1 1 1 1 14 007000h-0077ffh 2 0 0 0 0 0 1 1 1 0 13 006800h-006fffh 2 0 0 0 0 0 1 1 0 1 12 006000h-0067ffh 2 0 0 0 0 0 1 1 0 0 11 005800h-005fffh 2 0 0 0 0 0 1 0 1 1 10 005000h-0057ffh 2 0 0 0 0 0 1 0 1 0 9 004800h-004fffh 2 0 0 0 0 0 1 0 0 1 8 004000h-0047ffh 2 0 0 0 0 0 1 0 0 0 7 003800h-003fffh 2 0 0 0 0 0 0 1 1 1 6 003000h-0037ffh 2 0 0 0 0 0 0 1 1 0 5 002800h-002fffh 2 0 0 0 0 0 0 1 0 1 4 002000h-0027ffh 2 0 0 0 0 0 0 1 0 0 3 001800h-001fffh 2 0 0 0 0 0 0 0 1 1 2 001000h-0017ffh 2 0 0 0 0 0 0 0 1 0 1 000800h-000fffh 2 0 0 0 0 0 0 0 0 1 0 0 000000h-0007ffh 2 0 0 0 0 0 0 0 0 0
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 9 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 product selector guide product number en39sl160ah/l speed option full voltage range: vcc=1.65 ? 1.95 v -70 -90 max access time, ns ( t acc ) 70 90 max ce# access, ns ( t ce ) 70 90 max oe# access, ns ( t oe ) 30 35 block diagram we # ce# oe# state control comma nd register erase voltage generator input/output buffers pr ogra m vo lta ge generator chip enable output enable logic data latch y-decoder x-decoder y-gating cell matrix timer vcc detector a0-a19 vcc vss dq0 -dq 15 address latch block protect switches stb stb wp#/acc reset#
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 10 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 3. operating modes 16m flash user mode table operation ce# oe# we# reset# wp#/ acc a0-a19 (note 1) dq0-dq15 read l l h h l / h a in d out write l h l h (note 1) a in d in cmos standby v cc 0.2v x x v cc 0.2v x x high-z output disable l h h h x x high-z hardware reset x x x l x x high-z temporary block unprotect x x x v id (note 1) a in d in block group protect (note 2) l h l v id x block address, a6 =l, a1 = h, a0 = l d in chip unprotect (note 2) l h l v id (note 1) block address, a6 =l, a1 = h, a0 = l d in l=logic low= v il , h=logic high= v ih , v id = v hh =10.0 1.0v, x=don?t care (either l or h, but not floating!), d in =data in, d out =data out, a in =address in, notes: 1. if wp#/acc = v il , the first or last blocks are protected. if wp#/acc = v ih the first or last block protection depends on whether they were last protected or unprotected. if wp#/acc = v hh , all blocks will be unprotected. 2. please refer to ?block group protection and chip unprotection ?, flowchart 7a and flowchart 7b. table 4. device identifi ction (autoselect codes) 16m flash manufacturer/device id table note: 1. if a manufacturing id is read with a8=l, the chip will output a configuration code 7fh. a further manufacturing id must be read with a8=h. 2. a9 = v id is for hv a9 autoselect mode only. a9 must be vcc (cmos logic level) for command autoselect mode. description ce# oe# we# a19 to a12 a11 to a10 a9 2 a8 a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 1ch manufacturer id: eon l l h x x v id h 1 l xlxll x 7fh device id (top boot block) l l h x x v id x x l x l h 27h 4ah device id (bottom boot block) l l h x x v id x x l x l h 27h 4bh x 01h (protected) block protection verification l l h sa x v id xxlxhl x 00h (unprotected)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 11 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 user mode definitions standby mode the en39sl160ah/l has a cmos-compatible standby mode, which reduces the current to < 0.2a (typical). it is placed in cmos-compatible standby when the ce# pin is at v cc 0.2. reset# pin must also be at cmos input levels. if ce# and reset# are held at v ih , but not within v cc 0.2v, the device will be in the standby modes, but the st andby current will be grea ter. the outputs are in a high-impedance state independent of the oe# input. read mode the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors/blocks, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more additional information. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see the ?reset command? additional details. output disable mode when the oe# pin is at a logic high level (v ih ), the output from the en39sl160ah/l is disabled. the output pins are placed in a high impedance state. auto select identification mode the autoselect mode provides manufacturer and device identification, and block protection verification, through identifier codes output on dq15?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id ( 9.0 v to 11.0 v) on address pin a9. address pins a8, a6, a1, and a0 must be as shown in autoselect codes table. in addition, when verifying block protection, the block address must appear on the appropriate highest order address bits. refer to the corresponding block address tables. the command definitions table shows the remaining address bits that are don?t-care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15?dq0. to access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v id . see ?command definitions? for details on using the autoselect mode. write mode write operations, including programming data and erasing sectors/blocks of memory, require the host system to write a command or command sequence to the device. write cycles are initiated by placing the word address on the device?s address inputs while the data to be written is input on dq[15:0] in word mode. the host system must drive the ce# and we# pins low and the oe# pin high for a valid write operation to take place. all addresses are latched on the falling edge of we# and ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. the system is not required to provide further controls or timings. the device automatically provides internally generated program / erase
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 12 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 pulses and verifies the programmed /erased cells? margin. the host system can detect completion of a program or erase operation by re ading the dq[7] (data# polling) an d dq[6] (toggle) status bits. the ?command definitions? section of this document provides details on the specific device commands implemented in the en39sl160ah/l. reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at vss0.3 v, the device draws cmos standby current (icc2). if reset# is held at v il but not within vss0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. block group protection and chip unprotection the hardware block group protection feature disables both program and erase operations in any block. the hardware chip unprotection feature re-enables both program and erase operations in previously protected blocks. a block group implies three or four adjacent blocks that would be protected at the same time. please see the following tables which show the organization of block groups. there are two methods to enable this hardware protection circuitry. the first one requires only that the reset# pin be at v id and then standard microprocessor timings can be used to enable or disable this feature. see flowchart 7a and 7b for the algorithm and figure 12 for the timings. when doing chip unprotect, all the other blocks should be protected first. the second method is meant for programming equipment. this method requires v id be applied to both oe# and a9 pin and non-standard microprocessor timings are used. this method is described in a separate document called en39sl160ah/l supplement, which can be obtained by contacting a representative of eon silicon solution, inc.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 13 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 5. block group organization for (un)protection (block group 5~9) address range block group block sector (x16) 511 0ff800h-0fffffh ?. ?. 9 31 496 0f8000h-0f87ffh 495 0f7800h-0f7fffh ?. ?. 30 480 0f0000h-0f07ffh 479 0ef800h-0effffh ?. ?. 29 464 0e8000h-0e87ffh 463 0e7800h-0e7fffh ?. ?. 8 28 448 0e0000h-0e07ffh 447 0df800h-0dffffh ?. ?. 27 432 0d8000h-0d87ffh 431 0d7800h-0d7fffh ?. ?. 26 416 0d0000h-0d07ffh 415 0cf800h-0cffffh ?. ?. 25 400 0c8000h-0c87ffh 399 0c7800h-0c7fffh ?. ?. 7 24 384 0c0000h-0c07ffh 383 0bf800h-0bffffh ?. ?. 23 368 0b8000h-0b87ffh 367 0b7800h-0b7fffh ?. ?. 22 352 0b0000h-0b07ffh 351 0af800h-0affffh ?. ?. 21 336 0a8000h-0a87ffh 335 0a7800h-0a7fffh ?. ?. 6 20 320 0a0000h-0a07ffh 319 09f800h-09ffffh ?. ?. 19 304 098000h-0987ffh 303 097800h-097fffh ?. ?. 18 288 090000h-0907ffh 287 08f800h-08ffffh ?. ?. 17 272 088000h-0887ffh 271 087800h-087fffh ?. ?. 5 16 256 080000h-0807ffh
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 14 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 5. block group organization for (un)protection (block group 0~4) address range block group block sector (x16) 255 07f800h-07ffffh ?. ?. 15 240 078000h-0787ffh 239 077800h-077fffh ?. ?. 14 224 070000h-0707ffh 223 06f800h-06ffffh ?. ?. 13 208 068000h-0687ffh 207 067800h-067fffh ?. ?. 4 12 192 060000h-0607ffh 191 05f800h-05ffffh ?. ?. 11 176 058000h-0587ffh 175 057800h-057fffh ?. ?. 10 160 050000h-0507ffh 159 04f800h-04ffffh ?. ?. 9 144 048000h-0487ffh 143 047800h-047fffh ?. ?. 3 8 128 040000h-0407ffh 127 03f800h-03ffffh ?. ?. 7 112 038000h-0387ffh 111 037800h-037fffh ?. ?. 6 96 030000h-0307ffh 95 02f800h-02ffffh ?. ?. 5 80 028000h-0287ffh 79 027800h-027fffh ?. ?. 2 4 64 020000h-0207ffh 63 01f800h-01ffffh ?. ?. 3 48 018000h-0187ffh 47 017800h-017fffh ?. ?. 2 32 010000h-0107ffh 31 00f800h-00ffffh ?. ?. 1 1 16 008000h-0087ffh 15 007800h-007fffh ?. ?. 0 0 0 000000h-0007ffh
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 15 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 write protect / accelerated program (wp# / acc) the wp#/acc pin provides two functions. the write protect (wp#) function provides a hardware method of protecting the first or last 64k-byte block. the acc function allows faster manufacturing throughput at the factory, using an external high voltage. when wp#/acc is low, the device protects the first or last 64k-byte block; no matter the blocks are protected or unprotected using the method described in ?block/block group protection & chip unprotection?, program and erase operations in these blocks are ignored. when wp#/acc is high, the device reverts to the previous protection status of the first or last 64k-byte block. program and erase operations can now modify the data in the first or last 64k-byte block unless the block is protected using block protection. when wp#/acc is raised to v hh the memory automatically enters the accelerated program mode, this mode permit the system to skip the normal command unlock sequences and program byte/word locations directly to reduces the time required for program operation. when wp#/acc returns to v ih or v il normal operation resumes. the transitions from v ih or v il to v hh and from v hh to v ih or v il must be slower than t vhh , see figure 14 note that the wp#/acc pin must not be left floating or unconnected. in addition, wp#/acc pin must not be at v hh for operations other than accelerated programming. it could cause the device to be damaged. never raise this pin to v hh from any mode except read mode. otherwise the memory may be left in an indeterminate state. a 0.1f capacitor should be connected between the wp#/acc pin and the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during accelerated program mode. temporary block unprotect this feature allows temporary unprotection of previously protected block groups to change data while in-system. the block unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected blocks can be programmed or erased by simply selecting the block addresses. once is removed from the reset# pin, all the previously protected blocks are protected again. see accompanying figure and timing diagrams for more details. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30ns. the automatic sleep mode is independent of the ce#, we# and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output is latched and always available to the system. icc 5 in the dc characteristics table represents the automatic sleep mode current specification. start reset#=v id (note 1) perform erase or program operations reset#=v ih temporary block unprotect completed ( note 2 ) notes: 1. all protected blocks unprotected. 2. previously protected blocks protected again.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 16 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 common flash interface (cfi) the common flash interface (cfi) sp ecification outlines device and ho st systems software interrogation handshake, which allows specific ve ndor-specified software algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and backward-compatible for the specifie d flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 6-8. in word mode, the upper address bits (a7?msb) must be all zeros. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode and the system can read cfi data at the addresses given in tables 6?8. the system must write the reset command to re turn the device to the autoselect mode. table 6. cfi query identification string (1) adresses (word mode) adresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) 1. refer to cfi publication 100 for more details. table 7. system interface string addresses (word mode) addresses (byte mode) data description 1bh 36h 0016h vcc min (write /erase) dq7-dq4: volts, dq3 ?dq0: 100 millivolts 1ch 38h 0020h vcc max (write /erase) dq7-dq4: volts, dq3 ?dq0: 100 millivolts 1dh 3ah 0000h vpp min. voltage (00h = no vpp pin present) 1eh 3ch 0000h vpp max. voltage (00h = no vpp pin present) 1fh 3eh 0004h typical timeout per single byte/word program 2^n s 20h 40h 0000h typical timeout for min, size buffer write 2^n s (00h = not supported) 21h 42h 000ah typical timeout per individual sector/block erase 2^n ms 22h 44h 0000h typical timeout for full chip erase 2^n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2^n times typical 24h 48h 0000h max. timeout for buffer write 2^n times typical 25h 4ah 0004h max. timeout per individual sector/block erase 2^n times typical 26h 4ch 0000h max timeout for full chip erase 2^n times typical (00h = not supported)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 17 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 8. device geometry definition addresses (word mode) addresses (byte mode) da ta description 27h 4eh 0015h device size = 2^n byte 28h 29h 50h 52h 0002h 0000h flash device interface description; 0002h = x8/x16 asynchronous interface. 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2^n (00h = not supported) 2ch 58h 0002h number of erase sector/block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 00ffh 0001h 0010h 0000h erase sector region 1 information (y+1 = number of sectors; z x 256b = sector size) y = 511 + 1 = 512 sectors (01ffh = 511) z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) 31h 32h 33h 34h 62h 64h 66h 68h 001fh 0000h 0000h 0001h erase block region 2 information (y+1 = number of blocks; z x 256b = block size) y = 31 + 1 = 32 blocks (001fh = 31) z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the command definitions table. additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during vcc power up and power down transitions, or from system noise. low v cc write inhibit when vcc is less than v lko , the device does not accept any write cycles. this protects data during vcc power up and power down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until vcc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when vcc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih , or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. if ce#, we#, and oe# are all logical zero (not recommended usag e), it will be co nsidered a read. power-up write inhibit during power-up, the device automatically resets to read mode and locks out write cycles. even with ce# = v il , we# = v il and oe# = v ih , the device will not accept comma nds on the rising edge of we#.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 18 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 command definitions the operations of en39sl160ah/l are selected by one or more commands written into the command register to perform read/reset memory, read id, read block protection, program, sector/block erase, chip erase, erase suspend and erase resume. commands are made up of data sequences written at specific addresses via the command register. the sequences for the specified operation are defined in the command definitions table (table 9). incorrect addresses, incorrect data values or improper sequences will reset the device to read mode. table 9. en39sl160ah/l command definitions bus cycles 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle 5 th cycle 6 th cycle command sequence cycles addr data addr data addr data addr data addr data addr data read 1 ra rd reset 1 xxx f0 000 7f word 555 2aa 555 100 1c 000 7f manufacturer id byte 4 aaa aa 555 55 aaa 90 200 1c word 555 2aa 555 x01 274a device id top boot byte 4 aaa aa 555 55 aaa 90 x02 4a word 555 2aa 555 x01 274b device id bottom boot byte 4 aaa aa 555 55 aaa 90 x02 4b xx00 word 555 2aa 555 (ba) x02 xx01 00 autoselect block protect verify byte 4 aaa aa 555 55 aaa 90 (ba) x04 01 word 555 2aa 555 program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 555 2aa 555 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa block erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 ba 50 word 555 2aa 555 555 2aa sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend 1 xxx b0 erase resume 1 xxx 30 word 55 cfi query byte 1 aa 98 address and data values indicated in hex ra = read address: address of the memory location to be read. this is a read cycle. rd = read data: data read from location ra during read operation. this is a read cycle. pa = program address: address of the memory location to be programmed. x = don?t-care pd = program data: data to be programmed at location pa ba = block address: address of the block to be erased or ve rified. address bits a19-a15 uniquely select any block sa = sector address: address of the sector to be erased or verified. address bits a19-a11 uniquely select any sector
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 19 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 reading array data the device is automatically set to reading array data after power up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. following an erase suspend command, erase suspend mode is entered. the system can read array data using the standard read timings, with the only diff erence in that if it reads at an address within erase suspended sectors/blocks, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. the reset command must be issued to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see next section for details on reset. reset command writing the reset command to the device resets the device to reading array data. address bits are don?t- care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset comma nds until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a block is protected. the command definitions table shows the address and data requirements. this is an alternative to the method that requires v id on address bit a9 and is intended for prom programmers. two unlock cycles followed by the autoselect command initiate the autoselect command sequence. autoselect mode is then entered and the system may read at addresses shown in table 4 any number of times, without needing another command sequence. the system must write the reset command to exit the autoselect mode and return to reading array data. programming command programming the en39sl160ah/l is performed by using a four bus-cycle operation (two unlock write cycles followed by the program setup command and program data write cycle). when the program command is executed, no additional cpu controls or timings are necessary. an internal timer terminates the program operation automa tically. address is latched on the falling edge of c e# or we#, whichever is last; data is latched on the rising edge of ce# or we#, whichever is first. programming status may be checked by sampling data on dq7 (data# polling) or on dq6 (toggle bit). when the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. note that data can not be programmed from a 0 to a 1. only an erase operation can change a data from 0 to 1. when programming time limit is exceeded, dq5 will produce a logical ?1? and a reset co mmand can return the device to read mode.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 20 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 chip erase command chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded chip erase algorithm are ignored. the system can determine the status of the erase operation by using dq7, dq6, or dq2. see ?write operation status? for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. flowchart 4 illustrates the algorithm for the erase oper ation. see the erase/progra m operations tables in ?ac characteristics? for parameters, and to the chip, sector/block erase operation timings for timing waveforms. sector/block erase command sequence sector/block erase is a six bus cycle operation. the sector/block erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector/block to be erased, and the sector/block erase command. the command definitions table shows the address and data requirements for the sector/block erase command sequence. once the sector/block erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to ?write operation status? for information on these status bits. flowchart 4 illustrates the algorithm for the erase operation. refer to the erase/prog ram operations tables in the ?ac characteristics? section for parameters, and to the sector/block erase operations timing diagram for timing waveforms. erase suspend / resume command the erase suspend command allows the system to interrupt a sector/block erase operation and then read data from, or program data to, any sector/block not selected for erasure. this command is valid only during the sector/block erase operation. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. addresses are don?t-cares when writing the erase suspend command. when the erase suspend command is written during a sector/block erase operation, the device requires a maximum of 20 s to suspend the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector/block not selected for erasure. (the device ?erase suspends? all sector/blocks selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors/blocks produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector/block is actively erasing or is erase-suspended. see ?write operation status? for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors/blocks. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the autoselect command is not supported during erase suspend mode.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 21 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 the system must write the erase resume command (address bits are don?t-care) to exit the erase suspend mode and continue the sector/block erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. write operation status dq7: data# polling the en39sl160ah/l prov ides data# polling on dq7 to indicate th e status of the embedded operations. the data# polling feature is active during the embedde d programming, sector/block erase, chip erase, and erase suspend. (see table 6) when the embedded programming is in progress, an attempt to r ead the device will produce the complement of the data last written to dq7. upon the completion of the embedded programming, an attempt to read the device will produce the true da ta written to dq7. for the embedded programming, data# polling is valid after the rising edge of the four th we# or ce# pulse in the four-cycle sequence. when the embedded erase is in prog ress, an attempt to read the devi ce will produce a ?0? at the dq7 output. upon the completion of th e embedded erase, the device will pr oduce the ?1? at the dq7 output during the read cycles. for chip eras e, the data# polling is valid after th e rising edge of the sixth we# or ce# pulse in the six-cycle sequence. data# polling is va lid after the last rising edge of the we# or ce# pulse for chip erase or sector/block erase. data# polling must be performed at any address wi thin a sector/block that is being programmed or erased and not a protected sector/block. otherwise, data# polling may give an inaccurate result if the address used is in a protected block. just prior to the completion of the embedded operations, dq7 may change asynchronously when the output enable (oe#) is low. this means that the device is driving status information on dq7 at one instant of time and valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status of valid data. even if the device has completed the embedded operations and dq7 has a valid data, the data output on dq0-dq6 may be still invalid. the valid data on dq0-dq7 will be read on the subsequent read attempts. the flowchart for data# polling (dq7) is shown on flowchart 5. the data# polling (dq7) timing diagram is shown in figure 8. dq6: toggle bit i the en39sl160ah/l provides a ?toggle bit? on dq6 to indicate to the host system the status of the embedded programming and erase operations. (see table 6) during an embedded program or erase operation, successive attempts to read data from the device at any address (by active oe# or ce#) will result in dq6 to ggling between ?zero? and ?one?. once the embedded program or erase operation is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during embedded programming, the toggle bit is valid after the rising edge of the fourth we# pulse in the four-cycle sequence. during erase operation, the toggle bit is valid after the rising edge of the sixth we# pulse for sector/block erase or chip erase. in embedded programming, if the block being written to is protec ted, dq6 will toggles for about 2 s, then stop toggling without the data in the block having changed. in sector/block erase or chip erase, if all selected blocks are protected, dq6 will toggle for about 100 s. the chip will then re turn to the read mode without changing data in all protected blocks. the flowchart for the toggle bit (dq6) is shown in flowchart 6. the toggle bit timing diagram is shown in figure 9 .
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 22 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed. since it is possible that dq5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the dq6 is toggling after detecting a ?1? on dq5. the dq5 failure condition may appear if the system trie s to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector/block erase timer after writing a sector/block erase command sequence, the output on dq3 can be used to determine whether or not an erase operation has begun. (the sector/block erase timer does not apply to the chip erase command.) when sector/block erase starts, dq3 switches from ?0? to ?1.? this device does not support multiple sector/block erase command sequences so it is not very meaningful since it immediately shows as a ?1? after the first 30h command. future devices may support this feature. dq2: erase toggle bit ii the ?toggle bit? on dq2, when used with dq6, indicates whether a particular sector/block is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector/block is erase- suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses with in those sectors/blocks that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector/block is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors/blocks are selected for erasure. thus, both status bits are required for sector/block and mode information. refer to the following table to compare outputs for dq2 and dq6. flowchart 6 shows the toggle bit algorithm, and the section ?dq2: toggle bit? explains the algorithm. see also the ?dq6: toggle bit i? subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to flowchart 6 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 23 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of flowchart 6). write operation status operation dq7 (note2) dq6 dq5 (note1) dq3 dq2 (note2) embedded program algorithm dq7# toggle 0 n/a no toggle standar d mode embedded erase algorithm 0 toggle 0 1 toggle reading within erase suspended sector/block 1 no toggle 0 n/a toggle reading within non-erase suspended sector/block data data data data data erase suspend mode erase-suspend program dq7# toggle 0 n/a n/a 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. see ?dq5:exceeded timing limits? for more information. 2. dq7 and dq2 require a valid address when reading status i nformation. refer to the appropriate subsection for further details .
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 24 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 10. status register bits dq name logic level definition ?1? erase complete or erase sector/block in erase suspend ?0? erase on-going dq7 program complete or data of non-erase sector/block during erase suspend 7 data# polling dq7# program on-going ?-1-0-1-0-1-0-1-? erase or program on-going dq6 read during erase suspend 6 toggle bit ?-1-1-1-1-1-1-1-? erase complete ?1? program or erase error 5 time out bit ?0? program or erase on-going ?1? erase operation start 3 erase time out bit ?0? erase timeout period on-going ?-1-0-1-0-1-0-1-? chip erase, sector/block erase or erase suspend on currently addressed sector/block. (when dq5=1, erase error due to currently addressed sector/block. program during erase suspend on-going at current address 2 toggle bit dq2 erase suspend read on non erase suspend sector/block notes: dq7 data# polling: indicates the p/e c status check during program or erase, and on completion before checking bits dq5 for program or erase success. dq6 toggle bit: remains at constant level when p/e operations are complete or erase suspend is acknowledged. successive reads output complementary data on dq6 while programming or erase operation are on-going. dq5 time out bit: set to ?1? if failure in programming or erase dq3 sector/block erase command timeout bit :operation has started. only possible command is erase suspend (es). dq2 toggle bit: indicates the erase status and allows identification of the erased sector/block
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 25 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 embedded algorithms flowchart 1. embedded program star t write program comma nd sequence (shown below) dat a# p oll d evic e las t a ddress? programming done increment address no ye s verify data? yes no flowchart 2. embedded program command sequence see the command definitions section fo r more information on word mode. 2aah / 55h 555h / aah 555h / a0h program address / program data
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 26 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 flowchart 3. embedded erase flowchart 4. embedded erase command sequence see the command definitions section fo r more information on word mode. start write erase command sequence data poll from system or toggle bit successfully completed erase done data =ffh? yes no
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 27 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 flowchart 5. data# polling algorithm notes: (1) this second read is necessary in case the first read was done at the exact instant when the status data was in transition. flowchart 6. toggle bit algorithm notes: (2) this second set of reads is necessary in case the first set of reads wa s done at the exact instant when the status data was in transition. no yes dq6 = toggle? dq5 = 1? dq6 = toggle? no no yes yes read data twice start read data twice (2) fail pass no no dq7 = data? dq5 = 1? dq7 = data? yes yes no yes read data start read data (1) fail pass
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 28 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 flowchart 7a. in-system block group protect flowchart start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? no temporary block unprotect mode yes set up block group address remove v id from reset# write reset command block protect complete block group protect algorithm protect another block? yes reset plscnt = 1 no plscnt = 25? increment plscnt no device failed yes to protect: write 60h to block addr with a6 = 0, a1 = 1, a0 = 0 wait 150 s to verify: write 40h to block group address with a6 = 0, a1 = 1, a0 = 0 read from block address with a6 = 0, a1 = 1, a0 = 0 data = 01h? no yes wait 0.4 s
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 29 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 flowchart 7b. in-system chip unprotect flowchart start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? temporary block unprotect mode no yes all blocks protected? yes no protect all blocks: the indicated portion of the block protect algorithm must be performed for all unprotected blocks prior to issuing the first block unprotect address (see diagram 7a.) set up first block address chip unprotect: write 60h to block address with a6 = 1, a1 = 1, a0 = 0 wait 15 ms verify chip unprotect: write 40h to block address with a6 = 1, a1 = 1, a0 =0 read from block address with a6 = 1, a1 = 1, a0 = 0 data = 00h? no plscnt = 1000? no increment plscnt yes device failed last block verified? no set up next block address remove v id from reset# write reset command chip unprotect com p lete chip unprotect algorithm wait 0.4 s yes yes
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 30 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 11. dc characteristics (t a = - 40c to 85c or - 45c to 125c; v cc = 1.65-1.95v) notes 1. reset# pin input buffers are always enabled so that they draw power if not at full cmos supply voltages. 2. maximum i b cc b specifications are tested with vcc = vcc max. symbol parameter test conditions min typ max unit i li input leakage current 0v v in vcc 3 a i lo output leakage current 0v v out vcc 3 a active read current (byte mode) 5 10 ma i cc1 active read current (word mode) ce# = v il , oe# = v ih , f=5mhz 5 10 ma supply current (standby) ce# = reset# = vcc (note 1) 0.2 5.0 a i cc2 supply current (standby) for automotive (-45 c to +125 c) ce# = reset# = vcc (note 1) 0.2 15 a vcc , reset current ce# = reset# = vss 0.2 v (note 1) 0.2 5.0 a i cc3 vcc , reset current for automotive (-45 c to +125 c) ce# = reset# = vss 0.2 v (note 1) 0.2 15 a i cc4 supply current (program or erase) program or erase in progress 15 25 ma automatic sleep mode v ih = vcc 0.2 v v il = vss 0.2 v 0.2 5.0 a i cc5 automatic sleep mode for automotive (-45 c to +125 c) v ih = vcc 0.2 v v il = vss 0.2 v 0.2 15 a v il input low voltage -0.5 0.3 x vcc v v ih input high voltage 0.7 x vcc vcc + 0.3 v v ol output low voltage i ol = 100 a 0.1 v v oh output high voltage i oh = -100 a, vcc - 0.1 v v id a9 voltage (electronic signature) 9.0 10.0 11.0 v i id a9 current (electronic signature) a9 = v id 50 a v lko supply voltage (erase and program lock-out) 1.2 1.5 v
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 31 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 test conditions test specifications test conditions -70 -90 unit output load capacitance, c l 30 pf input rise and fall times 5 ns input pulse levels 0.0-2.0 v input timing measurement reference levels 1/2 vcc v output timing measurement reference levels 1/2 vcc v
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 32 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 ac characteristics hardware reset (reset#) (t a = - 40c to 85c or - 45c to 125c; v cc = 1.65-1.95v) speed parameter std description test setup -70 -90 unit t rp1 reset# pulse width (during embedded algorithms) min 10 us t rp2 reset# pulse width (not during embedded algorithms) min 500 ns t rh reset# high time before read min 50 ns t ready1 reset# pin low (during embedded algorithms) to read or write max 20 us t ready2 reset# pin low (not during embedded algorithms) to read or write max 500 ns figure 2. ac waveforms for reset# reset# timings
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 33 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 ac characteristics table 12. ac characteristics (t a = - 40c to 85c or - 45c to 125c; v cc = 1.65-1.95 v) read-only operations characteristics parameter symbols speed options jedec standard description test setup -70 -90 unit t avav t rc read cycle time min 70 90 ns t avqv t acc address to output delay ce# = v il oe# = v il max 70 90 ns t elqv t ce chip enable to output delay oe# = v il max 70 90 ns t glqv t oe output enable to output delay max 30 35 ns t ehqz t df chip enable to output high z max 20 ns t ghqz t df output enable to output high z max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns read min 0 ns t oeh output enable hold time toggle and data# polling min 10 ns notes: 1. high z is not 100% tested. 2. for ? 70, 90 vcc =1.65 ? 1.95v output load : 30pf input rise and fall times: 5ns input rise levels: 0.0 v to vcc timing measurement reference level, input and output: 1/2 vcc figure 3. ac waveforms for read operations addresses ce# oe# we# outputs t b acc t b rc b addresses stable t b oe b high z output valid t b ce b t b oh t b df t b oeh b high z
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 34 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 13. ac characteristics (t a = - 40c to 85c or - 45c to 125c; v cc = 1.65-1.95v) write (erase/program) operations parameter symbols speed options jedec standard description -70 -90 unit t avav t wc write cycle time (note 1) min 70 90 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 45 ns t dvwh t ds data setup time min 30 40 ns t whdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 45 ns t whdl t wph write pulse width high min 20 25 ns t whwh1 t whwh1 programming operation (note 2) typ 8 s sector typ 0.09 s block typ 0.18 s t whwh2 t whwh2 erase operation (note 2) chip typ 4 s t vcs vcc setup time (note 1) min 50 s notes: 1. not 100% tested. 2. see erase and programming performance for more information.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 35 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 14. ac characteristics (t a = - 40c to 85c or - 45c to 125c; v cc = 1.65-1.95v) write (erase/program) operations alternate ce# controlled writes parameter symbols speed options jedec standard description -70 -90 unit t avav t wc write cycle time (note 1) min 70 90 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 30 40 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to ce# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 45 ns t ehel t cph ce# pulse width high min 20 ns t whwh1 t whwh1 programming operation (note 2) typ 8 s sector typ 0.09 s block typ 0.18 s t whwh2 t whwh2 erase operation (note 2) chip typ. 4 s notes: 1. not 100% tested. 2. see erase and programming performance for more information.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 36 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 table 15. erase and programming performance limits parameter typ max unit comments sector erase time 0.09 0.4 sec block erase time 0.18 2 sec chip erase time 4 35 sec excludes 00h programming prior to erasure word programming time 8 200 s chip programming time 8 11 sec excludes system level overhead erase/program endurance 100k cycles minimum 100k cycles table 16. data retention parameter description test conditions min unit 150c 10 years data retention time 125c 20 years
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 37 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 ac characteristics figure 4. ac waveforms for chip erase operations timings notes: 1. va=valid address for reading status, d out = true data at read address. 2. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. v cc a ddresses ce# oe# we# data t c h t g hwl t cs t wph t wp t whwh2 t dh t d s 0x55 0x10 status d ou t t v cs erase command sequence (last 2 cycles) read status data (last two cycles) t w c t a s t ah 0x2aa 0x555 v a v a
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 38 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 ac characteristics figure 5. ac waveforms for block erase operations timings notes: 1. ba=block address (for block erase) , va=valid address for reading status, d out =true data at read address. 2. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. v cc a ddresses ce# oe# we# data t c h t g hwl t cs t wph t wp t whwh2 t dh t d s 0x55 0x50 status d ou t t v cs erase command sequence (last 2 cycles) re ad status data (last two cycles) t w c t a s t ah 0x2aa b a v a v a
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 39 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 figure 6. ac waveforms for s ector erase operations timings notes: 1. sa=sector address (for sector erase) , va=valid address for reading status, d out =true data at read address. 2. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. v cc a ddresses ce# oe# we# data t c h t g hwl t cs t wp h t wp t whwh2 t dh t d s 0x55 0x30 status d ou t t v cs erase command sequence (last 2 cycles) read status data (last two cycles) t w c t a s t ah 0x2a a s a v a v a
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 40 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 figure 7. program operation timings notes: 1. pa=program address, pd=program data, d out is the true data at the program address. 2. v cc shown in order to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. t vcs d out status pd oxa0 t ds t dh t whwh1 t ah t as t wc 0x555 pa pa pa program command sequence (last 2 cycles) program command sequence (last 2 cycles) t ghwl data v cc we# addresses ce# oe# t ch t wph t cs t wp
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 41 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 figure 8. ac waveforms for /data po lling during embedded algorithm operations notes: 1. va=valid address for reading data# polling status data 2. this diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle. figure 9. ac waveforms for toggle bit during embedded algorithm operations t o eh t df t o e t c e t c h t a cc t r c v a v a v a t o h valid data true com p lement comple -ment status data status data true valid data ce# addresses oe# we# dq[7] dq[6:0] t c e t o e t c h valid data valid status valid status valid status (first read) (second read) (stops toggling) a ddresses ce# oe# we# dq6, dq2 t r c t a cc v a v a v a v a t o eh t df t o h
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 42 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 figure 10. alternate ce# controlled write operation timings notes: pa = address of the memory location to be programmed. pd = data to be programmed at byte address. va = valid address for reading program or erase status d out = array data read at va shown above are the last two cycles of the program or erase command sequence and the last status read cycle reset# shown to illustrate t rh measurement references. it cannot occur as shown during a valid command sequence. figure 11. dq2 vs. dq6 we# dq6 dq2 enter embedded erase erase suspend enter erase suspend program erase resume erase enter suspend read enter suspend program erase erase complete erase suspend read t rh t wh t ghel t cp t bus y t ds t dh d out status pd for program 0x30 for sector erase 0x50 for block erase 0x10 for chip erase 0xa0 for program 0x55 for erase t cph t ws t whwh1 / t whwh2 addresses we# oe# ce# data reset# t ah t as t wc va pa for program sa for sector erase ba for block erase 0x555 for chip erase 0x555 for program 0x2aa for erase
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 43 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 figure 12. block group protect and chip unprotect timing diagram notes: use standard microprocessor timings for this device for read and write cycles. for block group protect, use a6=0, a1=1, a0=0. for chip unprotect, use a6=1, a1=1, a0=0. temporary block unprotect speed option unit parameter std description -70 -90 t vidr v id rise and fall time min 500 ns t rsp reset# setup time for temporary block unprotect(note) min 4 s notes: t rsp is not 100% tested. v id sa, a6,a1,a0 reset# 0 v t vidr t vidr >1
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 44 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 figure 13. temporary block unprotect timing diagram write protect / accelerated program figure 14. accelerated program timing diagram t rsp v id 0 or 2 v t vidr 0 or 2 v t vidr reset# ce# we#
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 45 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 figure 15. 48l tfbga 6mm x 8mm package outline min. nor max a - - - - - - 1.30 a1 0.23 0.29 - - - a2 0.84 0.91 - - - d 7.90 8.00 8.10 e 5.90 6.00 6.10 d1 - - - 5.60 - - - e1 - - - 4.00 - - - e - - - 0.80 - - - b 0.35 0.40 0.45 dimension in mm symbol note : 1. coplanarity: 0.1 mm
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 46 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 figure 16. 48l wfbga 4mm x 6mm package outline note : controlling dimensions are in millimeters (mm).
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 47 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 absolute maximum ratings parameter value unit storage temperature -65 to +150 plastic packages -65 to +125 ambient temperature with power applied -55 to +125 output short circuit current 1 200 ma a9, oe#, reset# 2 -0.5 to +11.0 v all other pins 3 -0.5 to vcc+0.5 v voltage with respect to ground vcc -0.5 to + vcc+0.5 v notes: 1. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. 2. minimum dc input voltage on a9, oe#, reset# pins is ?0.5v. during voltage transitions, a9, oe#, reset# pins may undershoot v ss to ?1.0v for periods of up to 50ns and to ?2.0v for periods of up to 20ns. see figure below. maximum dc input voltage on a9, oe#, and reset# is 9.0v which may overshoot to 11v for periods up to 20ns. 3. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, inputs may undershoot v ss to ?1.0v for periods of up to 50ns and to ?2.0 v for periods of up to 20ns. see figure below. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 1.5 v for periods up to 20ns. see figure below. 4. stresses above the values so mentioned above may cause permanent damage to the device. these values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. recommended operating ranges 1 parameter value unit ambient operating temperature industrial devices automotive devices -40 to 85 -45 to 125 operating supply voltage vcc full voltage range: 1.65 to 1.95 v 1. recommended operating ranges define those limits between which the functionality of the device is guaranteed. vcc +2.0v maximum negative overshoot waveform maximum positive overshoot waveform 0 0
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 48 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 purpose eon silicon solution inc. (hereinaft er called ?eon?) is going to prov ide its products? top marking on ics with < cfeon > from january 1st, 2009, and without any change of the part number and the compositions of the ics. eon is still keeping the pr omise of quality for all the products with the same as that of eon delivered before. please be advised with the change and appreciate your kindly cooperation and fully support eon?s product family. eon products? new top marking cfeon top marking example: for more information please contact your local sales office for additional information about eon memory solutions. cfeon part number: xxxx-xxx lot number: xxxxx date code: xxxxx
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 49 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 ordering information en39sl160a h - 70 b i p packaging content p = rohs compliant temperature range i = industrial (-40 c to +85 c) a = automotive (-45 c to +125 c) package b = 48-ball thin fine pitch ball grid array (tfbga) 0.8mm pitch, 6mm x 8 mm package n = 48-ball very-very-thin-profile fine pitch ball grid array (wfbga) 0.5mm pitch, 4mm x 6 mm package speed 70 = 70ns 90 = 90ns sector for write protect (wp#/acc=l) h = highest address block protected l = lowest address block protected base part number en = eon silicon solution inc. 39sl = 1.8v serial 4kbyte uniform-sector flash 160 = 16 megabit (1024k x 16) a = version identifier the valid combinations of en39sl160a. base part number sector for write protect (wp#/acc=l) speed package temperature packaging content h 70 b, n i p en39sl160a l 70 b, n i p h 90 b, n a p en39sl160a l 90 b, n a p
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi. com or modifications due to changes in technical specifications. 50 en39sl160ah/l rev. c, issue date: 2011 / 09 / 15 revisions list revision no description date a initial release 2010/10/15 b 1. add speed option of 90ns. 2. add temperature option of automotive (-45c to +125c). 3. update ordering information on page 49. 2011/02/23 c correct the typo for the connection diagrams of wfbga on page 3. 2011/09/15

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